The invention relates to a polyphase static var compensator (SVC) arrangement for use in controlling vars and regulating the supply voltage in, for example, high-voltage supply systems.
Static var compensators are known in which a series circuit comprising a capacitor bank, a switch and a current-limiting or damping reactor is connected across the supply system, the switch being controlled to switch the capacitor bank into or out of circuit according to the demands of the system. Such a series circuit is shown in FIG. 1.
The energy levels involved m AC systems to which such circuits are connected often require the series circuits to take currents of thousands of amperes and the switches to withstand voltage levels of perhaps twenty thousand volts or more. Where, as is common, thyristor valves are employed as the switch, it is not presently possible to obtain thyristors individually rated for these conditions and consequently the switch comprises a thyristor valve assembly consisting of a number of thyristors in series and, in certain cases, a number of paths in parallel. Each series device or parallel group of devices is commonly referred to as a "level"). Thyristors of the type in question are expensive and it is desirable to limit the numbers as far as possible. However, it is essential that the thyristors be able to withstand the voltage levels that may arise during switching operations, which voltages may be considerably in excess of those obtaining in steady state conditions, especially as a result of the turn-off or blocking operation.
The series circuit illustrated in FIG. 1, which is known as a thyristor switched capacitor (TSC) circuit, may be connected between one phase V of, say, a three phase system and star-point/neutral N, as shown, or may be one arm of a delta arrangement connected between two phases. The capacitor C and thyristor valve T are the basic components, the reactor L being provided to limit the peak current and also the rate of change of current in normal turn-on and under fault conditions.
FIG. 1 shows the thyristor valve T as comprising a reverse-parallel pair of thyristors to provide conduction in both directions. When the switch is closed, a control means (not shown) provides gating pulses at 90.degree. after the zero voltage crossings, so maintaining the thyristor valve in an unblocked (turned-on) condition. In this condition, as current falls to zero in one of the thyristors it is picked up smoothly in the other. A problem, however, arises when the thyristor valve is switched off (blocked). Referring to FIG. 2, the valve voltage is zero up to a time T.sub.1, while the voltage drop across the capacitor is in phase with, but exceeds, the system voltage (V) by between about 5 and 13% to counteract the antiphase voltage across the reactor L.
At a suitable zero current transition, e.g. T.sub.1, the thyristor valve is blocked. At this point the capacitor is fully charged, the charge is trapped and the capacitor voltage persists at its peak value as shown in FIG. 2 (negative upper electrode/positive lower electrode). One half-cycle after the valve is blocked, the supply voltage reaches its positive peak value, the upper capacitor electrode is taken to the same voltage and the lower electrode is thereby driven excessively positive, to a value equal to the trapped capacitor voltage plus the supply voltage. This combined voltage on the lower electrode, amounting to more than twice the supply peak voltage, is applied across the thyristor valve which would, in the absence of any relieving facility, have to be rated accordingly. The resulting large excursions of the valve voltage are shown in FIG. 2.
FIG. 3 shows the basic TSC circuit of FIG. 1 employed in a three-phase delta configuration to provide an SVC coupled to an AC system for the control of, for example, system voltage. The delta-connected TSC arrangement 10 is fed from the line terminals of the secondary windings 11 (which are shown, purely for the sake of illusion, as delta-connected) of a transformer 12. The primary windings 13 of the transformer 12 are shown connected together at an earthed neutral point to forms again purely for the sake of example, a star connection to the AC system (not shown).
A mode of operation of the TSC arrangement of FIG. 3 during blocking is illustrated in FIG. 4. This diagram shows, in turn, waveforms for system AC voltage, current through the thyristor valves, voltage across the TSC capacitors (or capacitor banks) and voltage across the valves. At times T.sub.1, T.sub.2 and T.sub.3, respectively, the valves for limbs ab, bc and ca may be switched off, i.e. blocked, again at zero-current points as shown in FIG. 2, and large voltage excursions appear across the valves as described in the single-phase case shown in FIG. 2. Other blocking sequences are possible which may affect the polarities, but not the magnitudes, of the trapped charge voltages.
An arrangement for reducing the voltage load on a thryistor switch in such a switched-capacitor compensator circuit is disclosed in EP-A-0 116 275, published Aug. 22, 1984. In this arrangement the capacitor of each phase of the compensator can be shunted by a resistor in series with an inductor or the winding of a transformer. When the capacitor is connected to an AC power system the inductor or transformer is unsaturated and presents a high impedance to the capacitor, whereas when the thyristor switch is opened the inductor or transformer is caused to go into saturation so that its reactance decreases and a large capacitor discharge current can then flow. The arrangement utilises separate, independently functioning discharge circuits for each phase.
The present application of the invention is directed to reducing the afore-mentioned undesirably large voltage excursions and preventing the thyristor valves having to hold off excessively high applied voltages in their blocked condition.